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Types

All types in openocd-python are frozen dataclasses — they are immutable after construction. Nothing mutable leaves the API surface. Import them from the top-level package:

from openocd import (
TargetState, Register, FlashSector, FlashBank,
TAPInfo, JTAGState, MemoryRegion, BitField,
DecodedRegister, Breakpoint, Watchpoint, RTTChannel,
)

Snapshot of target execution state, returned by target.halt(), target.step(), target.state(), and target.wait_halt().

@dataclass(frozen=True)
class TargetState:
name: str
state: Literal["running", "halted", "reset", "debug-running", "unknown"]
current_pc: int | None = None
FieldTypeDefaultDescription
namestr(required)Target name (e.g. stm32f1x.cpu)
stateLiteral[...](required)One of "running", "halted", "reset", "debug-running", "unknown"
current_pcint | NoneNoneProgram counter (populated only when halted)

A single CPU register, returned by registers.read_all().

@dataclass(frozen=True)
class Register:
name: str
number: int
value: int
size: int
dirty: bool = False
FieldTypeDefaultDescription
namestr(required)Register name (e.g. r0, pc, xPSR)
numberint(required)Register number in OpenOCD’s numbering
valueint(required)Current register value
sizeint(required)Register width in bits (typically 32)
dirtyboolFalseWhether the register has been modified but not committed

One sector inside a flash bank.

@dataclass(frozen=True)
class FlashSector:
index: int
offset: int
size: int
protected: bool
FieldTypeDescription
indexintSector number within the bank
offsetintByte offset from the bank base address
sizeintSector size in bytes
protectedboolTrue if write protection is enabled

A flash bank reported by OpenOCD, returned by flash.banks() and flash.info().

@dataclass(frozen=True)
class FlashBank:
index: int
name: str
base: int
size: int
bus_width: int
chip_width: int
target: str
sectors: list[FlashSector] = field(default_factory=list)
FieldTypeDefaultDescription
indexint(required)Bank number
namestr(required)Bank name (e.g. stm32f1x.flash)
baseint(required)Base address in memory
sizeint(required)Total bank size in bytes
bus_widthint(required)Bus width
chip_widthint(required)Chip width
targetstr(required)Associated target or driver name
sectorslist[FlashSector][]Sector list (populated only by flash.info())

One TAP discovered on the JTAG chain, returned by jtag.scan_chain().

@dataclass(frozen=True)
class TAPInfo:
name: str
chip: str
tap_name: str
idcode: int
ir_length: int
enabled: bool
FieldTypeDescription
namestrFull dotted name (e.g. stm32f1x.cpu)
chipstrChip portion of the name (e.g. stm32f1x)
tap_namestrTAP portion of the name (e.g. cpu)
idcodeintDetected IDCODE value
ir_lengthintInstruction register length in bits
enabledboolWhether the TAP is enabled in the scan chain

Enum of all 16 IEEE 1149.1 TAP controller states. Used with jtag.pathmove().

class JTAGState(str, Enum):
RESET = "RESET"
IDLE = "IDLE"
DRSELECT = "DRSELECT"
DRCAPTURE = "DRCAPTURE"
DRSHIFT = "DRSHIFT"
DREXIT1 = "DREXIT1"
DRPAUSE = "DRPAUSE"
DREXIT2 = "DREXIT2"
DRUPDATE = "DRUPDATE"
IRSELECT = "IRSELECT"
IRCAPTURE = "IRCAPTURE"
IRSHIFT = "IRSHIFT"
IREXIT1 = "IREXIT1"
IRPAUSE = "IRPAUSE"
IREXIT2 = "IREXIT2"
IRUPDATE = "IRUPDATE"

JTAGState is a str enum, so each member’s .value is its name as a string.

A chunk of memory read from the target.

@dataclass(frozen=True)
class MemoryRegion:
address: int
size: int
data: bytes
FieldTypeDescription
addressintStart address of the region
sizeintSize of the region in bytes
databytesRaw memory contents

One decoded bitfield inside a register, part of DecodedRegister.fields.

@dataclass(frozen=True)
class BitField:
name: str
offset: int
width: int
value: int
description: str
FieldTypeDescription
namestrField name from the SVD (e.g. ODR0)
offsetintBit offset within the register
widthintField width in bits
valueintExtracted field value
descriptionstrDescription from SVD metadata

A register value decoded into named bitfields via SVD, returned by svd.read_register() and svd.decode().

@dataclass(frozen=True)
class DecodedRegister:
peripheral: str
register: str
address: int
raw_value: int
fields: list[BitField] = field(default_factory=list)
FieldTypeDefaultDescription
peripheralstr(required)Peripheral name (e.g. GPIOA)
registerstr(required)Register name (e.g. ODR)
addressint(required)Memory-mapped address
raw_valueint(required)Raw 32-bit value
fieldslist[BitField][]Decoded bitfields, sorted by bit offset

DecodedRegister implements __str__ for formatted output:

GPIOA.ODR @ 0x4001080C = 0x00000001
[ 0:0] ODR0 = 0x1 Port output data bit 0
[ 1:1] ODR1 = 0x0 Port output data bit 1

Multi-bit fields show the range (e.g. [7:4]), single-bit fields show just the offset (e.g. [0] displayed as [ 0:0]).

An active breakpoint, returned by breakpoints.list().

@dataclass(frozen=True)
class Breakpoint:
number: int
type: Literal["hw", "sw"]
address: int
length: int
enabled: bool
FieldTypeDescription
numberintBreakpoint index
typeLiteral["hw", "sw"]Hardware or software breakpoint
addressintInstruction address
lengthintInstruction length in bytes (2 = Thumb, 4 = ARM)
enabledboolWhether the breakpoint is active

An active data watchpoint, returned by breakpoints.list_watchpoints().

@dataclass(frozen=True)
class Watchpoint:
number: int
address: int
length: int
access: Literal["r", "w", "rw"]
FieldTypeDescription
numberintWatchpoint index
addressintWatched memory address
lengthintSize of watched region in bytes
accessLiteral["r", "w", "rw"]Access type: read, write, or both

An RTT channel descriptor, returned by rtt.channels().

@dataclass(frozen=True)
class RTTChannel:
index: int
name: str
size: int
direction: Literal["up", "down"]
FieldTypeDescription
indexintChannel number
namestrChannel name (e.g. Terminal)
sizeintBuffer size in bytes
directionLiteral["up", "down"]up = target-to-host, down = host-to-target